With the rapid operation of electronic equipment, the EMI in the electronic equipment becomes a problem and the reduction of the EMI is required. As one technology for reducing the EMI in electronic equipment, a method employing a spread spectrum clock signal has been proposed. More specifically, jitter is intentionally generated so that a peak of a spectrum may not be generated at a particular frequency, or a frequency is varied gradually with a cycle, that provides no influence on the operation of the circuit, for example, a cycle in a range from several of kilo Hertz to several hundreds of kilo Hertz.
FIG. 17 is a functional block diagram showing a configuration of a clock signal generator disclosed in Japanese Patent Application Publication JP-A-2001-148690. As shown in FIG. 17, the above-mentioned clock signal generator has a clock generating unit 2001 for generating m-phase clock signals S1m having a desired frequency and phases shifted by a constant interval between adjacent two clock signals, a selector unit 2003 for selecting one of the m-phase clock signals S1m, and a dithering control unit 2002 for determining the selection in the selector unit 2003. The m-phase clock signals S1m generated in the clock generating unit 2001 are supplied to the selector unit 2003 and taken out via an output terminal 2005. To the selector unit 2003, a control signal SEL is supplied from the dithering control unit 2002. The selector unit 2003 sequentially selects one of the m-phase clock signals S1m in accordance with the control signal SEL and thus obtained clock signal S2 can be taken out from an output terminal 2004. The dithering control unit 2002 for controlling the selector unit 2003 generates a selection signal SEL such that the spectrum of the clock signal S2 obtained at the output terminal 2004 may spread over as wide as possible.
FIG. 18 is a circuit block diagram showing a specific configuration example of the dithering control unit 2002. As shown in FIG. 18, the dithering control unit 2002 includes eight D-type flip-flops 2031 to 2038 forming a serial ring, and three OR circuits 2041 to 2043. When one signal of output signals S0 to S4 is at a high level, other four signals are made to be at low level, and the high-level moves among these signals per cycle of a clock signal CK.
FIG. 19 is a block diagram showing a specific configuration example of the selector unit 2003. The selector unit 2003 includes five switch circuits 2051 to 2055 and a buffer circuit 2056. In synchronization with the above-mentioned output signals S0 to S4, one of five-phase clock signals DC0 to DC4 at ΔT intervals is selected, and a modulated clock signal is generated and outputted via the buffer circuit 2056.
FIG. 20 shows an operation waveform example of the above-mentioned clock signal generator. As shown in FIG. 20, in a time period A, the clock signals are selected in the order of DC0, DC1, DC2, SC3, DC4 and the period of the modulated clock signal S2 becomes T+ΔT. On the other hand, in a time period B, the clock signals are selected in the order of DC4, DC3, DC2, SC, DC0 and the period of the modulated clock signal S2 becomes T−ΔT. Here, “T” is defined as an inverse number of a frequency fCK of a system clock signal, and, hereinafter, “T” is used in the same sense. Since the operations in the time periods A and B are repeated, +ΔT and −ΔT are cancelled so that the modulation period Tmod (not shown) becomes Tmod=8×T. According to the above-mentioned clock signal generator, a clock signal can be outputted in which peaks on the spectrum are spread, and the EMI can be reduced by operating the electrical equipment employing the clock signal.
However, in the case where the above-mentioned clock signal generator is used, there is a problem as described below. The problem will be explained by referring to FIG. 21. FIG. 21 shows the problem in the operation of the above-mentioned clock signal generator. As shown in FIG. 21, when the edges of the m-phase clock signals S1m (a rising edge 2101 and a trailing edge 2103 are shown in FIG. 21) and the edges of the selection signal SEL overlap one another, the operations of the switch circuits 2051 to 2055 (switching between “0” and “1”) provided in the selector unit 2003 as shown in FIG. 19 becomes defective and the waveform of the modulated clock signal becomes deteriorated. That is, within 360 degrees as a clock phase corresponding to one period of the system clock signal as shown in FIG. 21 (the range shown by an arrow), a range of a clock phase of the system clock signal that can be actually changed is restricted to a range obtained by subtracting a range in consideration of a predetermined interval from 180 degrees, i.e., less than 180 degrees.
Here, referring to FIGS. 22A to 22C, the relationship between the modulation period and the spectrum intensity of the clock signal will be explained. FIG. 22A shows the relationship between the spectrum intensity and the frequency when the clock signal is not modulated. FIG. 22B shows the relationship between the spectrum intensity and the frequency when the modulation period is short, that is, 1/Tmod is large. FIG. 22C shows the relationship between the spectrum intensity and the frequency when the modulation period is long, that is, 1/Tmod is small. Here, “Tmod” represents a modulation period and “T” is an inverse number of the frequency fCK of the system clock signal.
As shown in FIG. 22A, when the clock signal is not modulated, a spectrum peak 2201 is observed in the position where f=1/T. In the case where the clock signal is modulated so that the modulation clock frequency may become T−ΔT and T+ΔT for spreading the spectrum as shown in FIG. 22A, peaks are expected to appear at frequencies f=1/(T+ΔT) and f=1/(T−ΔT). However, almost all spectrum components at frequencies f=1/(T+ΔT) and f=1/(T−ΔT) are concentrated at the peak 2201 at a frequency f=1/T when the modulation period is short, i.e., 1/Tmod>Δf, and the power dispersion never occurs as shown in FIG. 22B. Because, according to the nature of the Fourier transform, as to the waveform changing with a cycle of 1/Tmod, peaks appear at frequency intervals of 1/Tmod. On the other hand, when the modulation period is long as shown in FIG. 22C, i.e., 1/Tmod<Δf, the spectrum components at frequencies f=1/(T+ΔT) and f=1/(T−ΔT) appear as peaks. That is, in addition to the peak 2201 at the frequency f=1/T, a peak 2217 and a peak 2215 appear between the frequencies f=1/(T+ΔT) and f=1/(T−ΔT) at frequency intervals of 1/Tmod. With the power dispersion, the intensity of the peak 2201 at the frequency f=1/T becomes lower compared to the intensity of the peak 2201 as shown in FIGS. 22A and 22B, and the occurrence of power dispersion is seen.
Considering a condition under which the modulation effect is seen, it is necessary that the frequency interval at which the peaks appear is shorter than the frequency interval between 1/T and 1/(T+ΔT). That is, the following expression (1) is required to hold.1/Tmod<ABS(1/T−1/(T±ΔT))≈ΔT/T2  (1)Where ABS(X) represents an absolute value of X.
Here, given that the number of phases of multiphase clock signals is N, the modulation period Tmod is expressed by the following expression (2).Tmod=2N×T  (2)
With the expressions (1) and (2), the following expression (3) can be introduced.T/2<N×ΔT  (3)
Here, N×ΔT corresponds to the range in which the phase is valuable in the circuits as shown in FIGS. 17–19, and a phase valuable range of at least 180 degrees is required as described above.